This invention relates to a semiconductor integrated circuit device which has a reference current generating circuit independent particularly from a power supply voltage Vcc.
FIG. 1 is a circuit diagram showing the conventional reference current generating circuit. In this circuit, a P-channel MOS transistor Qp1, a N-channel MOS transistor Qn1, a resistor R1, and a N-channel MOS transistor Qn2 are connected in series between a power supply voltage Vcc and a ground GND. The gate of the transistor Qp1 is supplied with a starting signal Vstart for controlling the circuit to turn from the stand-by state to the active state. The gate of the transistor Qn1 is applied with a reference voltage Vref generated by the external circuit. The gate of the transistor Qn2 is connected to a drain thereof so as to constitute a diode. The transistor Qn2 outputs an output Vout from the gate to make a reference current Iref which is equal to the current flowing into Qn2 through the resistor R1, flow from a N-channel MOS transistor Qn6 (Qn6 has substantially the same characteristics and size as those of Qn2) which is connected to form a current mirror circuit with the transistor Qn2.
When the voltages at the both ends of the resistor R1 are respectively denoted as V1 and V2, the current value Iref is determined by the values of V1 and V2. In the circuit constituted as above, V1 depends on the reference voltage and the threshold voltage of the transistor Qn1, and V2 depends on the threshold voltage of the transistor Qn2. The potentials V1 and V2 are thus determined by the reference voltage Vref and the threshold voltages Vth of the transistors Qn1 and Qn2, as represented by the following equations:
V1=Vrefxe2x88x92VthV2=Vthxe2x80x83xe2x80x83(1)
Hence, the current value Iref is represented as follows:
Iref=(V1xe2x88x92V2)/R1=(Vrefxe2x88x922Vth)/R1xe2x80x83xe2x80x83(2)
where R1 is the resistance value of the resistor R1.
As is clear from the above equation (2), the current value Iref is represented by the equation which does not include the term of the power supply voltage Vcc. The current value Iref is determined by the reference voltage Vref, the threshold voltage Vth of the transistors, and the resistance value R1. This circuit is thus independent from the influence of the power supply voltage Vcc.
FIG. 2 is a circuit diagram showing the constitution of the conventional oscillation circuit using the reference current generating circuit shown in FIG. 1. This circuit is basically the same as that disclosed in U.S. Pat. No. 5,627,488. The elements shown in FIG. 1 are denoted by the same reference numerals.
A capacitor C1 has one end connected selectively to either of the power supply voltage Vcc and the drain of the N-channel MOS transistor Qn6 in accordance with the level of the voltage of the common gate of a N-channel transistor Qn45 and a P-channel transistor Qp20. Similarly, a capacitor C2 has one end connected selectively to either of the power supply voltage Vcc and the drain of the N-channel MOS transistor Qn7 in accordance with the voltage level of the common gate of a N-channel transistor Qn46 and a P-channel transistor Qp21.
P-channel MOS transistors Qp14-Qp16 and N-channel MOS transistors Qn38-Qn4O constitute a first amplifier A1 for comparing the reference voltage Vref and the voltage Vcap1 at the one end of the capacitor C1 to amplify and output the difference thereof. Similarly, P-channel MOS transistors Qp17-Qp19 and N-channel MOS transistors Qn41-Qn43 constitute a second amplifier A2 for comparing the reference voltage Vref and the voltage Vcap2 at the one end of the capacitor C2 to amplify and output the difference thereof.
NAND gates G1 and G2 constitute an order logic circuit for outputting the order logic of the two amplifiers. In accordance with the output of the order logic circuit, the voltage level of the common gate of the transistor Qn45 and the transistor Qp20 and the voltage level of the common gate of the transistor Qn46 and the transistor Qp21 are alternately set at xe2x80x9cHxe2x80x9d (high level) and xe2x80x9cLxe2x80x9d (low level).
The operation of the oscillation circuit of FIG. 2 will be described below.
In a stand-by state, the signal Vstart is set at xe2x80x9cHxe2x80x9d. In this time, the P-channel MOS transistors Qp1, Qp14, Qp17, and the N-channel MOS transistor Qn40 and Qn43 are turned off to shut the power supply system. While, the P-channel MOS transistor Qp13 and the N-channel MOS transistors Qn34, Qn35, and Qn36 are turned on, thereby the circuit is set at an initial state. In this time, the output from the NAND gate G2 is set at xe2x80x9cHxe2x80x9d and the output from the NAND gate G1 is set at xe2x80x9cLxe2x80x9d. In accordance with the outputs from the NAND gates, the voltage Vcap1 of the one end of the capacitor C1 is set at xe2x80x9cLxe2x80x9d, and the voltage Vcap2 of the one end of the capacitor C2 is set at xe2x80x9cHxe2x80x9d. The output VOSC of the oscillation circuit is thus set at xe2x80x9cLxe2x80x9d.
When the signal Vstart is turned from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, the oscillation starts: the P-channel MOS transistor Qp13 and the N-channel MOS transistors Qn34, Qn35, and Qn36 are turned off, in contrast, the P-channel MOS transistors Qp1, Qp14, Qp17, and the N-channel MOS transistors Qn40 and Qn43 are turned on. In this time, the reference current generating circuit and the differential amplifiers A1 and A2 are set in the active state.
In the oscillation starting state, Vcap1 is set at xe2x80x9cLxe2x80x9d with respect to Vref, and the differential amplifier A1 operates to drop the voltage level of a node N1. The output of the NAND gate G1 is thereby inverted to xe2x80x9cHxe2x80x9d. In contrast, Vcap2 is set at xe2x80x9cHxe2x80x9d with respect to Vref, and thus the other differential amplifier A2 operates to increase the voltage level of a node N2 to xe2x80x9cHxe2x80x9d, and the output of the NAND gate G2 is inverted to xe2x80x9cLxe2x80x9d (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at xe2x80x9cHxe2x80x9d).
When the NAND gate G1 outputs the signal at xe2x80x9cHxe2x80x9d level in the above-mentioned manner, the transistor Qn46 is turned on, thereby the capacitor C2 discharges the current Iref equal to the current flowing through the resistor R1 of the reference current generating circuit. Thus, the voltage level Vcap2 is dropped to a level lower than Vref, and the potential level of the node N2 is thus dropped to invert the output of the NAND gate G2 to xe2x80x9cHxe2x80x9d (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at xe2x80x9cLxe2x80x9d). While, the NAND gate G2 outputs xe2x80x9cLxe2x80x9d to turn on the transistor Qp20, and the capacitor C1 is charged to the power supply voltage Vcc. The potential level Vcap1 of the capacitor C1 is thus increased to increase the potential level of the node N1.
In this manner, the levels of G1 and G2 are stabilized at xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively, during a period from the time when Vcap2 is set at Vcc to the time when Vcap2 is dropped to Vref.
When the NAND gate G2 outputs xe2x80x9cHxe2x80x9d, the transistor Qn45 is turned on, and the capacitor C1 discharges the current Iref equal to the current flowing through the resistor R1 of the reference current generating circuit (in this time, the transistors Qn2, Qn6, and Qn7 have substantially the same characteristics and size). The voltage level Vcap1 of the capacitor C1 is dropped to a level lower than Vref, and the potential level of the node N1 is dropped to invert the output of the NAND gate G1 to xe2x80x9cHxe2x80x9d (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at xe2x80x9cHxe2x80x9d).
While, when the NAND gate G1 outputs xe2x80x9cLxe2x80x9d, the transistor Qp21 is turned on, and the capacitor C2 is charged to the power supply voltage Vcc thereby. The potential level Vcap2 of the capacitor C2 is thus increased to increase the potential level of the node N2. As described above, the levels of G1 and G2 are stabilized at xe2x80x9cLxe2x80x9d and xe2x80x9cHxe2x80x9d, respectively, during a period from the time when the Vcap1 is set at Vcc to the time when Vcap1 is dropped to Vref. In this manner, the oscillation circuit performs the oscillation by repeating such two states alternatively.
The circuits shown in FIGS. 1 and 2, however, has the problems as described below.
As represented in the equation (2), the circuit shown in FIG. 1 is free from the influence of the power supply voltage. The circuit of FIG. 1, however, depends on the threshold voltages Vth of the transistors Qn1 and Qn2, and thus the reference current is adversely affected by the variation of the threshold voltages of the transistors so much.
Assuming that the variation of the threshold voltage due to the variation generated in the manufacturing process of the transistors is xcex94Vth, the average value of the threshold voltage is Vth, the threshold voltage including the variation is Vthxe2x80x2, the relationship among them is represented as Vthxe2x80x2=Vth+xcex94Vth. In view of this relationship, the current value Iref is represented by the following equation:
Iref=(Vrefxe2x88x922Vthxe2x88x922xcex94Vth)/R1xe2x80x83xe2x80x83(3)
The proportion of variation Axcex94ref of the current value Iref due to the variation xcex94Vth of the threshold voltage to the current value Iref is represented as follows:
xe2x80x83xcex94Iref/Iref=2xcex94Vth/(Vrefxe2x88x922Vth)xe2x80x83xe2x80x83(4)
When Vref=2.4V, Vth=0.7V, and xcex94Vth=0.2V, the rate of the variation of the current is 0.4/1.0=40%. As is clear from this, the reference current generating circuit shown in FIG. 1 cannot generate the current affected little by the variation of the threshold voltage.
In addition, the oscillation circuit shown in FIG. 2 uses the reference current generating circuit shown in FIG. 1 as a power supply with use of the reference voltage Vref. In order to prevent he influence of the power supply, the reference voltage Vref is generally set within a scope from 1.0 to 1.5V. However, if Vref is decreased, the variation of the current value due to the variation of the threshold voltage will be increased, as represented in the equations (3) and (4). The reference current is deviated larger as Vref is decreased, even if the variation in the threshold voltage remains the same. In these days, the power supply voltage has been designed to be decreased. This problem therefore will not be ignored.
As described above, the current value Iref generated by the conventional reference current generating circuit is not affected by the power supply voltage, but is affected by the variation of the threshold voltages of the transistors in the circuit.
The operation of the oscillation circuit using such a reference current generating circuit is inevitably affected by the variation of the reference current value due to the variation of the threshold voltages. Further, even if the variation in the threshold voltage is not increased, the variation in the reference current value will be increased when the reference potential is decreased. Therefore, with such a reference current generating circuit, the reduction of the power supply voltage cannot be easily attained.
The object of the present invention is to provide a semiconductor integrated circuit device having an oscillation circuit which uses a circuit for generating a stable reference current independently from not only the influence of the power supply voltage but also the influence of the variation of the threshold voltages of the transistors related to the generation of the reference current.
The object of the present invention is attained by the semiconductor integrated circuit device, comprising: a reference current generating circuit including a first MOS transistor having a gate connected to a node having a first potential, a second MOS transistor having a gate and a drain connected to each other so as to constitute a diode, the gate and the drain of the second MOS transistor being connected to a node having a second potential, and a resistor connected between a source of the first MOS transistor and the drain of the second MOS transistor; and a level shifter including a third MOS transistor applied with the first potential from a power supply through a load element, the third MOS transistor having a drain and a gate connected to each other so as to constitute a diode, the drain and the gate of the third MOS transistor being connected to the node having the first potential, and a fourth MOS transistor having a gate and a drain connected to the source of the third MOS transistor so as to constitute a diode and applied with a reference voltage at its own source, wherein the third and fourth MOS transistors of the level shifter comprise transistors, the total sum of the threshold voltages of which is substantially equal to that of the threshold voltages of the first and second MOS transistors of the reference current generating circuit, and the third and fourth MOS transistors generate the reference current in the resistor of the reference current generating circuit in accordance with a voltage applied to the gate of the first MOS transistor.
As one modification of the above-mentioned constitution, the level shifter may comprise the third MOS transistor applied with the first potential from a power supply through a P-channel transistor as a load element, and having a drain and a gate connected to each other so as to constitute a diode, the drain and the gate being connected to the node having the first potential; the fourth MOS transistor constituted as a diode, which has a gate and a drain connected to the source of the third MOS transistor and a source connected to a drain of a N-channel MOS transistor load element; and a differential amplifier for controlling the P-channel MOS transistor load element and the N-channel MOS transistor load element by outputting a difference between the reference voltage and a potential at the source of the fourth MOS transistor.
According to the present invention, drops of the threshold voltages of the first and second MOS transistors are added to the reference voltage by using the third and fourth MOS transistors, the drop of the threshold voltages of which are equal to that of the threshold voltages of the first and second MOS transistors. With this constitution, the variation of the threshold voltage of the transistors, which may affect the reference current independent from the influence of the power supply voltage, can be compensated.
In the present invention, the level shifter increases the reference voltage by adding thereto the threshold voltages of the third and fourth MOS transistors in the level shifter in order to compensate the drops of the threshold voltages of the first and second MOS transistors. The stable reference current independent from the influence of the variation of the threshold voltages thereby can be supplied to the oscillation circuit. Such a constitution is incorporated into a semiconductor integrated circuit device, e.g. a non-volatile semiconductor memory device, which includes a circuit for performing an oscillation circuit by using a reference current.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinbefore and hereinafter.